In June 2025, PCI-SIG released the final PCIe 7.0 specification to its members. Just three years after PCIe 6.0, the new standard pushes per-lane speed from 64 GT/s to 128 GT/s, delivering a staggering 512 GB/s of bidirectional x16 bandwidth. First PCIe 7.0 hardware is expected between late 2026 and 2027. For AI data centers, this shatters the bandwidth ceiling for GPU interconnect, high-speed storage, and memory expansion once again — but for interconnect vendors, 128 GT/s is first and foremost a physics exam.

1. Key Metrics of PCIe 7.0

Unlike the coding-scheme revolution from PCIe 5.0 to 6.0, PCIe 7.0 takes a more pragmatic evolutionary path:

• 128 GT/s per lane: Continuing with PAM-4 encoding, doubling the symbol rate to double throughput. A x16 link delivers 512 GB/s bidirectional — four times PCIe 5.0, enough for bottleneck-free pairing of next-gen AI accelerators with 800G/1.6T networking.
• FLIT and FEC carry over: The FLIT (Flow Control Unit) transmission mode and Forward Error Correction introduced in PCIe 6.0 are retained and refined, providing the signal-integrity foundation for 128 GT/s.
• Backward compatible: Like every PCIe generation, 7.0 remains backward compatible with 6.0/5.0/4.0, so the existing ecosystem transitions smoothly. But "compatible" does not mean "painless" — the real challenges hide in the physical layer.

2. Speed Doubles, Interconnect Feels It First: The Copper Reach Limit

Every doubling of frequency roughly doubles copper insertion loss, and the 128 GT/s Nyquist frequency approaches 32 GHz. At these frequencies:

• Reach collapses: Unrepeated copper reach at PCIe 7.0 rates shrinks to extremely short distances — even slightly longer in-chassis routing can exceed the link budget. Riser cables and backplane traces take the hit first.
• Retimers become mandatory: In the PCIe 5.0 era, Retimers appeared only in long-reach scenarios; they became common in 6.0. In the 7.0 era, nearly any scenario beyond direct chip-to-chip connection needs Retimer-based signal conditioning. This changes cable assembly architecture — cables are no longer "passive" copper but active interconnect solutions co-designed with Retimers.
• Connectors become the new bottleneck: When cable bodies barely pass via material upgrades, connector impedance discontinuities and crosstalk often become the weakest link. Design margins for high-density connectors such as SlimSAS and MCIO are severely compressed at 128 GT/s.

3. Optical Aware Retimer: Optics Enters the Picture

Notably, alongside the PCIe 7.0 specification, PCI-SIG released the Optical Aware Retimer ECN (Engineering Change Notice), paving the way at the standards level for "PCIe over fiber" for the first time. This sends a clear signal:

• Rack-scale optical interconnect is on the agenda: For rack-level and cross-rack scenarios, fiber's ultra-low loss and EMI immunity are moving from "optional" to "required". AOCs (Active Optical Cables) paired with PCIe 7.0 will be a hot topic over the next two years.
• Copper is not out: Inside servers and for short reaches, copper's cost and power advantages remain unbeatable. The next 3–5 years will be an era of "copper + Retimer" coexisting with optical interconnect, selected per scenario — which is precisely the ultimate test of an interconnect vendor's selection and customization capabilities.

4. What This Means for Cable and Connector Vendors

128 GT/s raises the industry bar to a new height:

• Material upgrades: Ultra-low-loss dielectrics, silver-plated conductors, and precision shielding move from "premium options" to "table stakes". Material consistency directly determines mass-production yield.
• Simulation first: At 32 GHz, no experience-based design survives contact with reality. Full-link 3D EM simulation correlated against measured S-parameters becomes standard practice.
• Test and validation: 128 GT/s BER testing and jitter tolerance testing demand more from instruments and fixtures. Vendors who can show measured, repeatable data win a clear advantage in customer selection.

5. YZMU's Technology Roadmap

YZMU has already begun building reserves for the PCIe 7.0 era:

• High-frequency material validation: Evaluating next-generation low-loss cable material systems for 128 GT/s, with baseline insertion-loss and crosstalk testing across key frequency bands.
• Retimer co-design: Joint bring-up with mainstream Retimer solutions, exploring integrated "cable + Retimer" delivery to shorten customer system integration cycles.
• Connector optimization: High-frequency simulation optimization of key interfaces such as SlimSAS and MCIO, reserving design margin for next-generation speeds.
• Optical and copper in parallel: Tracking the Optical Aware Retimer ecosystem and building AOC-related capabilities to cover interconnect scenarios from in-chassis to rack-scale.